In order to prevent deterioration of hot carrier immunity due to fine fabrication of an element, an inverse T-type transistor has been proposed (for example, IEDM 86, pp. 742-745). The inverse T-type transistor is common with a transistor having an LDD structure in that a source and drain are formed by a dual layer composed of an N.sup.- layer and an N.sup.+ layer formed in a surface of a P-type silicon (Si) substrate and the N.sup.- layer faces a channel region while the inverse T-type transistor is different from the transistor having the LDD structure in that an overlap between a polycrystalline silicon layer constituting a gate electrode and the N.sup.- layer is larger.
Such a structure is formed in order to prevent deterioration of the current driving capability by electrons wrapped in a portion above the N.sup.- layer of an S.sub.i O.sub.2 layer which is a gate oxide layer. However, the inverse T-type transistor has an overlap capacitance of the gate electrode and the drain larger than that of the transistor having the LDD structure and accordingly operation of a circuit becomes slower.
In order to overcome this problem, an improved inverse T-type transistor has been proposed in, for example, "REDUCTION OF GATE OVERLAP CAPACITANCE OF INVERSE-T TRANSISTOR", Collected Papers of 51th Science Lecture Meeting of the Japan Society of Applied Physics Association, pp. 575, 26p-G-5, Autumn 1990. In the improved inverse T-type transistor, since a thickness of a layer of the portion above the N.sup.- layer of S.sub.i O.sub.2 layer constituting the gate oxide layer is thick, the overlap capacitance of the gate electrode and the drain is smaller as compared with the inverse T-type transistor.
However, the improved inverse T-type transistor has been studied only by a simulation, while its practical device structure and fabricating method are not disclosed.